1. Field of the Invention
The present invention relates to a field effect transistor (referred to hereinafter as a MOSFET) subjected to a silicidation process and a method of manufacturing the same.
2. Description of the Background Art
In the past, logic devices such as microprocessors and memory devices represented by a DRAM have been manufactured separately. In recent years, however, semiconductor devices have been more highly integrated, and such separately manufactured logic and memory devices have accordingly been mounted in a single chip (referred to as a hybrid logic-memory device).
Each of the logic and memory devices included in the hybrid logic-memory device comprises transistors. Most of the transistors in either device are MOSFETs. However, there is a difference in required characteristics between MOSFETs constituting a logic circuit and MOSFETs constituting a memory device. Therefore, there exists a difference in construction therebetween.
With reference to FIG. 10A, a MOSFET of a logic device comprises a well 2c in a semiconductor substrate not shown, a gate electrode 3c, a gate insulating film 4c and sidewalls 6 which are formed on the well 2c, and source/drain diffusion regions 7c and 8c formed in the well 2c. In many cases, the MOSFET of the logic device further comprises regions 11c, 12c, 13c of a compound of metal such as cobalt and silicon, i.e. silicide, which are formed in the surfaces of the gate electrode 3c and the source/drain diffusion regions 7c, 8c since the MOSFET of the logic device which is required to have a high driving capability must reduce the parasitic resistance of an electrode portion by means of the silicidation using metal. Silicidation of the surface of a diffusion region also has the effect of preventing spikes which are prone to occur when a contact interconnect line to the diffusion region is formed.
On the other hand, a MOSFET of a memory device (FIG. 10B) is similar to the MOSFET of the logic circuit in that it comprises a gate electrode 3a, a gate insulating film 4a and sidewalls 6 which are formed on a well 2a, and source/drain diffusion regions 7a, 8a formed in the well 2a. The MOSFET of the memory device, however, is constructed such that only the gate electrode 3a has a silicided region 23a, unlike the MOSFET of the logic device in which each of the electrode portions has a silicided region.
The gate electrode 3a is silicided for the above described reasons. The other electrode portions are not silicided to prevent a leakage current which is prone to flow from the source/drain diffusion regions 7a, 8a to the well 2a. A flow of the leakage current causes electric charges to flow out of a storage node of a capacitor connected to one of the source/drain diffusion regions 7a and 8a, resulting in the decrease in the ability of the capacitor to hold information. Silicidation using metal forms a new energy level in a band gap of silicon to increase the number of carriers in the electrode portions, thereby causing a leakage current to readily flow. For this reason, the source/drain diffusion regions 7a and 8a are not silicided.
A method of manufacturing MOSFETs of the above-mentioned hybrid logic-memory device is described with reference to FIGS. 11 through 16. Two regions in a right half of FIGS. 11 through 16 are defined as a memory device region as labeled "DRAM" in FIG. 11, and two regions in a left half thereof are defined as a logic device region as labeled "LOGIC" in FIG. 11. The process of formation of both N-type and P-type MOSFETs in each of the memory and logic device regions is illustrated.
Initially, isolation regions 5 are formed on the semiconductor substrate 1 by the LOCOS (LOCal Oxidation of Silicon) process and the like. A photoresist not shown is applied to the surface of the semiconductor substrate 1 and patterned. Using the patterned photoresist as a mask, impurities are implanted into the semiconductor substrate 1 to form the P-type wells 2a and 2c. Then, the photoresist is removed. Likewise, N-type wells 2b and 2d are formed (FIG. 11).
Next, the MOSFETs of the memory device are formed. Thermal oxidation of the surface of the wells 2a to 2d forms gate insulating films 4a to 4d, respectively. Phosphorus-containing polycrystalline silicon, for example, is deposited on the entire surfaces of the gate insulating films 4a to 4d and the isolation regions 5 by the low pressure CVD (referred to hereinafter as "LPCVD") process. Tungsten, for example, is deposited on the phosphorus-containing polycrystalline silicon. Then, heat treatment is performed to form a compound of tungsten and polycrystalline silicon, i.e. tungsten silicide. A silicon oxide film serving as a mask for the patterning of the polycrystalline silicon and tungsten silicide into the form of gate electrodes is deposited by the CVD process. A photoresist is applied and patterned. Using the photoresist as a mask, the silicon oxide film is etched. The photoresist is then removed. This provides patterned silicon oxide films 24a and 24b. Using the silicon oxide films 24a and 24b as a mask, etching is performed on the underlying structure to form a gate electrode including polycrystalline silicon 3a and tungsten silicide 23a and a gate electrode including polycrystalline silicon 3b and tungsten silicide 23b in the memory device region (FIG. 12). Such silicided polycrystalline silicon used for a gate electrode is referred to as polycide.
The N-type well 2b in the memory device region and the entire logic device region are covered with a photoresist. Phosphorus ions, for example, are implanted into the P-type well 2a in the memory device region by the ion implantation technique to form N.sup.- source/drain diffusion regions 9a for use in an LDD (Lightly Doped Drain) structure. Then, the photoresist is removed. Likewise, the P-type well 2a and the entire logic device region are covered with a photoresist, and boron ions, for example, are implanted into the N-type well 2b to form P.sup.- source/drain diffusion regions 9b for use in the LDD structure.
Then, the photoresist is removed. A silicon oxide film is deposited on the surface of the semiconductor substrate 1 and then etched back to form the sidewalls 6. Parts of the gate insulating films 4a and 4b which lie outside the sidewalls 6 are etched away at the same time. Thereafter, the N-type well 2b and the entire logic device region are covered again with a photoresist, and phosphorus ions are implanted into the P-type well 2a to form the N.sup.+ source/drain diffusion regions 7a and 8a. Then, the photoresist is removed. The P-type well 2a and the entire logic device region are covered again with a photoresist, and boron ions are implanted into the N-type well 2b to form P.sup.+ source/drain diffusion regions 7b and 8b. Then, the photoresist is removed (FIG. 13).
Prior to the next step of forming the MOSFETs in the logic device region, an oxidation-resistant silicon nitride film 25 is formed to cover the entire memory device region so that oxidation does not proceed in the memory device region (FIG. 14).
For the formation of the MOSFETs in the logic device region, impurity-free polycrystalline silicon is initially deposited on the entire surface of the semiconductor substrate 1 by the LPCVD process. A photoresist is patterned so that only part of the polycrystalline silicon which overlies the P-type well 2c in the logic device region is exposed. Phosphorus ions are implanted into the exposed part of the polycrystalline silicon to form N-type polycrystalline silicon. Then, the photoresist is removed. Likewise, a photoresist is patterned so that only part of the polycrystalline silicon which overlies the N-type well 2d is exposed, and boron ions are implanted into the exposed part of the polycrystalline silicon to form P-type polycrystalline silicon. Then, the photoresist is removed. A photoresist pattern for gate electrode shaping is formed. Using the photoresist pattern, the polycrystalline silicon is etched to form the N.sup.+ gate electrode 3c and a P.sup.+ gate electrode 3d. Different types of impurities are implanted into the gate electrodes between the N-type and P-type MOSFETs so as to control the threshold voltage levels of the respective MOSFETs. The photoresist pattern is removed. In the same manner as in the memory device region, N.sup.- source/drain diffusion regions 9c and N.sup.+ source/drain diffusion regions 7c, 8c are formed in the P-type well 2c, and sidewalls 6 are formed on the P-type well 2c. Similarly, P.sup.- source/drain diffusion regions 9d and P.sup.+ source/drain diffusion regions 7d, 8d are formed in the N-type well 2d, and the sidewalls 6 are formed on the N-type well 2d (FIG. 15).
The electrode portions of the logic device are silicided in the following manner. Cobalt, for example, is deposited on the surface of the semiconductor substrate 1 by the sputtering process. Heat treatment is performed to change the cobalt on the surfaces of the gate electrodes 3c, 3d and the source/drain diffusion regions 7c, 8c, 7d, 8d of the MOSFETs in the logic device region into cobalt silicide regions 11c, 12c, 13c, 11d, 12d, 13d. Unreacted cobalt remaining unsilicided is removed (FIG. 16). A silicon portion which is not exposed is not silicided in spite of heating. Such a portion silicided in a self-aligned manner is referred to as salicide (self aligned silicide).
Subsequently, the silicon nitride film 25 is removed, and the steps of forming an interlayer insulating film and forming interconnect lines are performed.
As above described, the MOSFETs constructed to conform to the logic device region and the memory device region, respectively, have conventionally been manufactured separately in the respective regions. However, the memory device region employs the polycide formation method whereas the logic device region employs the salicide formation method. This results in the increased number of process steps which are very complicated.
Further, cobalt silicide and nickel silicide which have a low resistivity are desirably used also for the gate electrodes of the MOSFETs of a memory device. However, a suitable method of removing these silicides have not yet been found, and the above-mentioned polycide formation method in which the entire surface of the substrate is silicided and patterned has not achieved the silicidation using cobalt and nickel.
Then, the use of the salicide formation method is desired when the MOSFETs in the memory device region are manufactured, as well as in the logic device region. Such a method of manufacturing a semiconductor device includes a technique disclosed in Japanese Patent Application Laid-Open No. P01-264257A (1989) which will be described below.
Initially, the isolation regions 5 are formed on the semiconductor substrate 1, and the wells 2a to 2d are formed (FIG. 11). The gate insulating films 4a to 4d are formed, and polycrystalline silicon is deposited on the entire surfaces of the gate insulating films 4a to 4d and the isolation regions 5 by the CVD process. A silicon nitride film is formed on the upper surface of the polycrystalline silicon. A photoresist is formed on the upper surface of the silicon nitride film and patterned. Using the photoresist, the gate electrodes 3a to 3d and silicon nitride films 26a to 26d are formed by etching (FIG. 17). Next, the source/drain diffusion regions 9a to 9d are formed using the silicon nitride films 26a to 26d and the gate electrodes 3a to 3d as a mask. Thereafter, a silicon oxide film is formed on the surface of the semiconductor substrate 1 by the CVD process, and the sidewalls 6 are formed on the side surfaces of the gate electrodes 3a to 3d by reactive ion etching (referred to hereinafter as RIE). The source/drain diffusion regions 7a to 7d, 8a to 8d are formed using the silicon nitride films 26a to 26d, the gate electrodes 3a to 3d and the sidewalls 6 as a mask. Parts of the gate insulating films 4c and 4d which lie outside the sidewalls 6 and the silicon nitride films 26a to 26d are selectively removed. A high-melting-point metal film such as tungsten is deposited on the entire surface of the semiconductor substrate 1 by sputtering. Thereafter, heat treatment is performed to silicide an exposed silicon surface. Thus, silicided regions 23a to 23d, 27c, 27d, 28c, 28d are formed. Unreacted high-melting-point metal film is removed (FIG. 18). Subsequently, an interlayer insulating film 22, a bit line 14, a storage node 15, an electrode 16 opposed to the storage node 15, and interconnect lines 17 to 21 are sequentially formed (FIG. 19). In general, an N-type MOSFET is often used for a memory cell in a memory device, and a P-type MOSFET is often used for a peripheral circuit such as a sense amplifier. Thus, the storage node 15, the bit line 14 and others are shown in FIG. 19 only for the N-type MOSFET in the memory device region.
The technique disclosed in Japanese Patent Application Laid-Open No. P01-264257A employs the salicide formation method in the manufacture of the MOSFETs in both the logic device region and the memory device region, and therefore requires a smaller number of process steps than a technique which employs both the salicide formation method and the polycide formation method, thereby being capable of performing silicidation relatively easily.
In this method, however, which part of the source/drain diffusion regions is to be silicided depends on which part of the gate insulating films 4a to 4d is to be removed. The gate insulating films 4a to 4d which are in general thinner than the gate electrodes 3a to 3d are prone to be removed together when the sidewalls 6 are formed by the RIE process. It is very difficult to control an RIE unit so that the gate insulating films 4a and 4b are left unetched in the memory device region but the gate insulating films 4c and 4d are partially etched away in the logic device region. Such a problem might be encountered when other dry etching processes and wet etching processes are employed.
A structural problem arises in addition to the problem in terms of the manufacturing method. MOSFETs manufactured by this manufacturing method are similar in construction to those of the background art shown in FIGS. 10A and 10B. Problematic herein is the silicidation of the gate electrode of the MOSFET used for a memory cell. This problem is described using the MOSFETs of FIG. 19 as an example. Since the gate electrode 3a having the entirely silicided surface has a low gate resistance, electric charges stored in the storage node 15 are liable to flow through the interlayer insulating film 22 into the silicided region 23a to generate a new leakage current (as indicated by the arrow Z). Such a leakage current, similar to the above-mentioned leakage current from the diffusion region to the substrate, causes the electric charges to flow out of the storage node 15 to decrease the ability of the capacitor to hold information.
An additional consideration with the construction of the MOSFET used for the memory cell is described below. The MOSFETs of FIG. 19 taken as an example in which the diffusion region 7a that is not connected to the storage node 15 is connected to the bit line 14 do not have the problem of the decrease in the information holding ability due to the leakage current. As a matter of fact, silicidation of the diffusion region 7a of FIG. 19 is rather better for the purpose of decreasing the resistance thereof.